Putting memory above a processor sounds like a simple way to save space. For a PCBA engineer, however, the real task is making two hidden solder interfaces form reliably during assembly. The packages must match mechanically and electrically, remain compatible as they heat up, and pass a test plan that can detect meaningful defects.
Package-on-Package (PoP) stacks separate semiconductor packages vertically, often placing memory above a logic device. Its main benefit is a smaller combined PCB footprint. Successful assembly depends on the specific package pair, controlled material deposition, a validated reflow profile, and inspection supported by electrical testing.
From our engineering perspective at XWONDER, a PoP review should begin before the production quote is finalized. In this guide, we explain how the stack works, where assembly risks develop, and what information helps turn a compact design into a buildable PCBA.
What Is Package-on-Package, and What Actually Gets Stacked?
PoP connects separately packaged devices through a vertical solder interface. In a typical logic-and-memory arrangement, the lower package contains the processor or system-on-chip, while the upper package contains memory. Solder connections on the underside of the lower package attach the assembly to the PCB.
The distinction between a package and a die matters. A memory package may already contain several dies inside it. Those internal dies do not make the board assembly a four-layer or eight-layer PoP stack. For the common two-package arrangement discussed here, the PCBA process must form the lower board connection and the upper package connection.
Separately packaged parts can be tested before they are joined. That helps with component selection and screening, but it does not prove that the finished stack will work. Assembly can introduce opens, bridges, or intermittent connections even when both incoming devices passed their supplier tests.
Why Use PoP Instead of Placing Logic and Memory Side by Side?
Less PCB area
Overlapping the two package footprints frees board area for other functions. The actual saving depends on package size, routing, and keep-out requirements.
Compact interconnects
The vertical connection can shorten logic-to-memory paths. Electrical performance still depends on the full package and system design.
Configuration options
Compatible memory options can support different product configurations. Every alternate must satisfy the processor and package requirements.
Footprint reduction does not mean automatic height reduction. A stacked assembly uses the vertical space above the lower package. The enclosure must accommodate its total height, solder stand-off, and mechanical tolerances. Heat flow, shielding, and any thermal interface material also need room.
We would assess PoP when PCB area is tight and a supported logic-and-memory pairing exists. A side-by-side layout may be easier to cool, inspect, or rework when board area is available. Neither architecture is the right answer for every product.
| Review item | PoP stack | Side-by-side packages |
|---|---|---|
| PCB footprint | Overlapping package area can save board space. | Separate footprints need more layout area. |
| Vertical clearance | Total stack height must fit the enclosure. | No package-on-package height addition. |
| Memory routing | Uses the supported package interface. | Requires board-level routing between devices. |
| Thermal design | Logic and memory are thermally coupled in the stack. | More flexibility to separate heat sources. |
| Assembly and repair | Two hidden interfaces complicate process review. | Packages can generally be accessed separately. |
How Does PoP Assembly Work on an SMT Line?
A common approach places both packages before one reflow cycle. Other routes use a preassembled stack or separate joining steps. The component supplier's assembly guidance and the qualified process should determine the route. Adding a top package is not simply an extra placement in an otherwise unchanged BGA recipe.
Review the package pair and PCB design
Check exact part numbers, package revisions, ball maps, dimensions, orientation, and assembly limits. Confirm that the upper interface of the logic package is intended for the selected memory package.
Prepare components and print solder paste
Review moisture handling and exposure records, then print paste onto the PCB lands for the lower package. The stencil, paste, and solder paste inspection criteria should suit the actual pitch and land pattern.
Place the lower package
Place the logic package on the printed PCB. Check vision settings, nozzle selection, board support, alignment, and placement force so the package sits correctly without disturbing the deposit.
Apply material to the upper package
A qualified process may dip the upper solder balls into flux or a suitable solder paste. Material selection, film depth, transfer consistency, and working life need control. Flux dipping and paste dipping are not interchangeable recipes.
Place the upper package and reflow
Align the memory package with the lower package's receiving pads. Reflow the stack using a measured profile that supports joint formation at both interfaces while respecting component and material limits.
Inspect, test, and release
Apply the agreed inspection and electrical test plan. Investigate defects by interface and location, and establish a stable pilot process before releasing the build for volume production.
Moisture control is part of this workflow. Track each package's moisture sensitivity level and handling history, and follow the applicable supplier instructions for drying when needed. The allowable package temperature is a limit, not an oven setting to copy. TI's MSL and reflow guidance explains why board profiles must also account for solder material recommendations and component ratings.
Why Is Package Warpage a Major PoP Assembly Risk?
Thin packages can change shape as temperature rises and falls. The upper package, lower package, and PCB may not bend in the same direction or by the same amount. Their relative movement affects whether the solder balls remain close enough to the mating pads while the solder is molten.
A stack that looks flat at room temperature can still develop a gap during reflow. If surfaces separate or do not wet properly, the result may be an open joint or a head-in-pillow defect, where the solder ball and mating solder fail to merge fully. Thermal movement is one possible cause; oxidation, material activity, and deposition also affect joint formation.
We would assess warpage against the selected package geometry and process window. There is no single micrometer limit that works for every PoP design. Temperature-dependent supplier data, or measurements using a suitable method such as shadow moire, can help explain behavior that incoming coplanarity checks miss.
Engineering checkpoint: Review how the two mating surfaces move relative to each other over the soldering cycle. An isolated room-temperature flatness value does not describe that interaction.
Which Other Process Variables Can Cause PoP Defects?
Warpage is only one part of the risk review. Inadequate material transfer, an unstable placement process, and an unsuitable thermal profile can create similar symptoms. A useful investigation links the defect to its location and process history before changing multiple settings at once.
| Risk | Possible consequence | Evidence to review |
|---|---|---|
| Inconsistent paste or flux transfer | Insufficient wetting, opens, or excess material | Deposit checks, dip settings, material condition, and supplier guidance |
| Placement offset or package movement | Misaligned contacts or bridges | Vision setup, placement records, force, and board support |
| Unsuitable reflow profile | Incomplete joining or thermal damage | Measured board profile, package limits, and material process window |
| Moisture exposure beyond limits | Package damage during heating | Dry-pack condition, exposure history, storage, and drying records |
| Unverified alternate memory | Mechanical fit problems or functional failure | Package drawings, interface requirements, and system validation |
How Should Hidden PoP Solder Joints Be Inspected?
Optical inspection can check visible features, but it cannot directly inspect the internal solder interfaces of a completed stack. X-ray is an important tool for assessing hidden joint geometry and identifying conditions such as bridges or abnormal solder distribution. Its effectiveness depends on the package, imaging setup, and defect type.
A clean 2D X-ray image does not prove that every joint has formed a sound metallurgical connection. Overlapping features can make interpretation difficult. Oblique views or 3D methods may help in selected cases, while destructive analysis may be needed to resolve a specific failure mechanism.
Electrical and functional tests add different evidence. Depending on available access and device support, the plan may include continuity checks, boundary scan, memory tests, boot checks, and operation across relevant conditions. Test coverage should be documented; passing a short boot test does not establish long-term reliability.
Inspect geometry
Use imaging to assess hidden solder features within the method's detection limits.
Verify function
Exercise the processor-memory interface with a defined test program and coverage.
Qualify reliability
Select environmental and mechanical validation according to the product's use conditions.
How Do Thermal Design and Advanced Packaging Change the Review?
A processor below memory creates a coupled thermal problem. Assess power dissipation, workload, ambient temperature, enclosure conditions, and available heat paths together. The goal is to keep both devices within their operating limits without creating unacceptable mechanical loading on the stack.
Fan-out technology is one route used in advanced PoP structures. TSMC's InFO platform includes InFO-PoP, combining fan-out integration with package stacking. Such developments change package construction, but they do not remove the need for part-specific assembly instructions and system validation.
Other forms of vertical integration, including stacked dies and through-silicon-via technologies, should not be treated as interchangeable names for PoP. For a PCBA review, the useful questions remain concrete: What arrives as a finished component? Which interfaces does the assembly process form? What evidence is required to release the finished board?
What Should You Ask a PCBA Partner Before a PoP Build?
From inside the XWONDER engineering function, our starting point for a PoP inquiry is the proposed package pair and its manufacturing requirements. Standard BGA placement capability alone does not establish that a particular PoP stack is qualified. The production route, process controls, inspection coverage, and test access need a project-specific review.
We would structure that review around three decisions: whether the package combination is supported, whether the process can be validated, and whether the acceptance plan can identify the relevant failures. These questions help separate a general assembly discussion from a production commitment.
- Package compatibility: Are the exact logic and memory parts approved to work together?
- Process readiness: Is the proposed material application and placement route suitable for those packages?
- Thermal evidence: How will reflow behavior and operating temperature be evaluated?
- Inspection and test: Which defects can the proposed methods detect, and where are the coverage gaps?
- Traceability and change control: Can the build be tied to component lots, materials, process revisions, and test results?
- Pilot release: What acceptance criteria, defect review, and rework rules apply before volume production?
What Information Should You Prepare for a PoP RFQ?
A BOM and board outline are useful, but they do not fully define a PoP assembly. Include package-level information and the intended operating conditions wherever possible. If an item is still open, identify it as an engineering question instead of allowing it to become an assumed requirement.
| Information to provide | What it helps establish |
|---|---|
| Logic and memory part numbers, package codes, and approved alternates | The exact package pair and substitution boundaries |
| Package drawings, ball maps, and supplier assembly guidance | Mechanical compatibility, orientation, and process constraints |
| PCB fabrication data, stack-up, BOM, and placement files | Board manufacturability and assembly setup |
| Moisture sensitivity and available warpage data | Handling controls and temperature-dependent joining risks |
| Enclosure height, thermal design, and operating conditions | Clearance and system-level validation needs |
| Firmware, test requirements, access points, and acceptance criteria | Inspection coverage and functional release requirements |
| Prototype quantity, expected volume, schedule, and rework policy | Pilot scope, production planning, and commercial assumptions |
What Do Buyers Commonly Ask About PoP Assembly?
Is PoP the same as BGA?
No. BGA describes a ball-grid-array interconnection format. PoP describes an arrangement of separate packages stacked together. A PoP assembly can use BGA-style connections at more than one interface.
Can any memory package be placed above a processor?
No. Package dimensions, ball pattern, electrical interface, power requirements, and supported memory configuration must match. A similar footprint is not proof of compatibility.
Does PoP always need a single reflow cycle?
No. Single-reflow stacking is one approach. A preassembled stack or another supplier-supported route may be appropriate. The selected route must account for the components' permitted thermal exposure and the assembly process.
Is underfill always required?
No. Its use depends on package guidance and the product's reliability requirements. Underfill can affect mechanical behavior and repair options, so it should be specified and validated rather than added by default.
Can a PoP assembly be reworked?
It may be possible, but feasibility depends on access, materials, package limits, and the condition of the board. An approved procedure and post-rework acceptance plan are needed before treating rework as a production recovery option.
Our engineering takeaway: PoP saves board area by moving integration into the vertical direction. Reliable PCBA production still depends on matching the package pair, controlling the joining process, and proving the finished assembly through an appropriate inspection and test plan.
Planning a PCBA Project with PoP Packages?
Share your BOM, package drawings, PCB files, and test requirements with XWONDER. Start with a project-specific discussion of assembly feasibility, process risks, and the information needed for a production plan.
Technical references: Texas Instruments: MSL Ratings and Reflow Profiles; TSMC: Integrated Fan-Out Packaging. Apply the documentation for the actual package, materials, and product requirements when defining an assembly process.
